1. Field of the Invention
The present description is related to the field of electric circuitry, and more specifically to an RFID tag circuit die with an additional file to control I/O bump flow.
2. Description of the Related Art
FIGS. 1A, 1B and 1C are snapshots of steps in methods for preparing integrated circuit chips from a silicon wafer according to embodiments.
Integrated circuits are made according to embodiments, using semiconductor fabrication methods. A quick overview of these methods is now described.
FIG. 1A shows a starting wafer 191. Wafer 191 is typically of semiconductor material, such as silicon. The silicon is sometimes doped with p-type or n-type impurities, to improve its electronic properties as desired. Wafer 191 has an original surface 192, at which circuits are formed as described below.
FIG. 1B shows a wafer 194, which is derived from wafer 192 after circuits 195 have been formed according to embodiments. Circuits 195 are formed by semiconductor manufacturing machines, often operated by foundries. It is worthwhile to note that circuits 194 are formed at surface 192, both beneath its original level and above it. Accordingly, wafer 194 has a new surface, which is elevated compared to original surface 192.
FIG. 1C shows that wafer 194 of FIG. 1B is afterwards separated into chips 197, 198, 199. Separation can happen by dicing wafer 194, or etching it, etc. Each of chips 197, 198, 199 typically contains one of circuits 195, and is thus called an integrated circuit (IC) chip or “circuit die”. The size of each IC chip is thus determined in part by the size of circuit 195.
FIGS. 2A through 2E demonstrate a particular problem with the state of the art of manufacturing circuit die for use in RFID tags. FIG. 2A shows a cross section of a completed wafer before it has been diced into multiple individual circuit die. FIG. 2A shows the wafer substrate 201 and the overlying layers 205 of wiring metallurgy and dielectric insulation. At the top of the processed wafer are bump pads 202a,b and test pad 203.
Bump pads 202a,b are “I/O” pads meaning they are used to support later manufactured “bumps” or “contacts” that supply electrical signals to and/or from the semiconductor die of which they are a part. As will be seen, pad 202a and pad 202b belong to two separate die (that is, pad 202a belongs to a first die and pad 202b belongs to second die). As will be observed further below, the bumps that are later formed on the I/O pads on an RFID tag circuit die are typically connected to an antenna assembly after the die has been separated from the wafer.
Also observed on the surface of the wafer is a test pad 203. The test pad is a form of I/O used by the wafer processing manufacturer (e.g., a foundry) to test the quality of the structures within wiring layer 205 and/or the quality of the transistors that are embedded within the substrate 201. Here, test structures, called test sites, are purposely created within the wiring layer 205 and the substrate 201 and pad 203 (among other pads like pad 203) are electrically to respective one or more test site(s). As will be seen, the wafer is cut into individual die by sawing through a region of the wafer at or near to the test pad 203.
The depiction of FIG. 2A shows the wafer after the wafer is near completion. Here, note that the pads 202a, 202b and 203 can be viewed as being “exposed” through a layer of passivation 204a, 204b, 204c, 204d. During the final stages of wafer processing, referred to as “back-end” processing, after the pads 202a, 202b, 203 are formed, a layer of passivation is coated over the wafer thereby covering the pads 202a, 202b, 203. The passivation layer is subsequently patterned such that openings in the passivation layer are formed directly above the pads 202a, 202b, 203 thereby exposing them.
FIG. 2B shows the beginning of the process of separating the wafer into individual die. According to the specific depiction of FIG. 2B, the wafer is sawed along a saw street 211 which, according to the particular depiction observed, is along the wafer test pad 203. The particular depiction observed also indicates that the wafer is not completely sawed through.
FIG. 2C next shows the formation of the aforementioned I/O bumps 206a, 206b. According to one process, the bumps 206a, 206b are made substantially of Nickel (Ni) and Gold (Au), e.g., NixAux-1, and are deposited by a plating process such as electroplating. According to other processes the bumps 206a, 206b may be made substantially of Au or Palladium (Pd) or solder. In a plating processing, the bumps are deposited on their respective bump pads by activating one or more chemical reactions between the exposed pads 202a, 202b and a liquid solution that is applied to the surface of the wafer. Depositing bumps in this fashion is well known in the art.
The liquid solution used to form the bumps, however, substantially wets the entire surface of the wafer causing chemical reaction at regions of the wafer other than the exposed pads 202a, 202b. Because the solution is designed to react with the metal of the bump pads 206a, 206b to form the bumps, other exposed metallic regions are apt to promote the deposition of bump material. Because the metallurgy associated with the wafer test pad 203 and the wiring layer 205 of the wafer may include metal that is the same as or similar to the metal of the bumps pads 202a, 202b, these regions tend to promote the formation of unwanted bump material 206c, 206d. Note that if the wafer is not sawed at all the test pad 203 by itself can support the formation of unwanted bump material.
FIG. 2D shows the next step in the process which entails the separation of the wafer into individual die. This can be done either by continuing the sawing or by “back-grinding” the back of the wafer until the surface of back of the wafer meets the end of the sawed to depth.
FIG. 2E shows a problem that is particularly acute with respect to RFID circuit die. According to the depiction of FIG. 2E, when the antenna assembly is attached to the circuit die, the antenna inlay 208a makes electrical contact (“shorts” 266) not only with the bump 206a (where electrical contact is supposed to be made) but also with the unwanted bump material. The antenna receives high frequency signals. Electrical channels that process the received high frequency signals are usually designed with an “impedance” that is precisely attuned to diminish the ill-effects of signal attenuation and/or reflections along the channel.
The impedance of an electrical channel is typically affected by the capacitances, inductances and/or resistances associated with the channel. Here, the contact between the inlay 208a and the unwanted bump material adversely affects these features of the channel such that the impedance of the channel deviates from its designed-for value. The result is a marginally operable or inoperable RFID tag.